1. Field of the Invention
The present invention relates to the field of semiconductor packaging, and more particularly, to 3-D semiconductor packaging.
2. Description of the Related Art
The conventional method for forming through silicon vias is described as follows. First, a plurality of grooves are formed on a first surface of a silicon substrate. An insulation layer is then formed on the side walls of the grooves by chemical vapor deposition, forming a plurality of accommodating rooms. The material used for the insulation layer is usually silicon dioxide. Then, the accommodating rooms are filled with a conductive metal, usually copper. Finally, the first surface and a second surface of the substrate are ground or etched so as to expose the conductive metal, thus a plurality of conductive vias are formed.
A notable disadvantage of the conventional approach is described as follows. When signals are transmitted, the energy loss of the signals will be relatively high while the signals pass through the conductive vias, so that the quality of transmission is poor.